DIG Course

Digital Course - VHDL and FPGA

Last updated: 05-11-09

This courses intended to cover digital design at several levels - hence will some of the material properly not be relevant for you
The textbook (s) mention below intended as backup when my descriptions become too superficial and poor.
Once you learned the basic elements of ISE, please feel free to try the examples of the books and the exercises as well.

Lecture

The history of digital design: Boolean algebra, TTL vs. CMOS, Programmable logic - CPLD vs. FPGA, Introduction to hardware description language.

Getting started - how to get: XiLinx ISE 11.1 WebPACK and Adapt suite from Digilent.

First digital design: Schematic - Synthesize - Pin assignment - Place&Route - Download.
Presentation of the BASYS / NEXYS2 board - What's behind: The Schematic and Inside the FPGA

First VHDL design: VHDL-Module - Entity and Architecture - In Out - STD_LOGIC
The basic elements in order to describe a simple digital design.

Test the kit - Most of the inputs and outputs will be tested - Schematic and VHDL design

First Test Bench: Component, Unit Under Test - UUT, wait for ..the ISIM simulator
The original purpose of VHDL was simulation, hence will the concept of testing be important for all your digital designs

Test Bench for a Full Adder
Combinatorial Logic - A short presentation of Combinatorial logic

Data types, Operators and Attributes: STD_LOGIC, STD_LOGIC_VECTOR, INTEGER, AND, OR, NOT, NAND, NOR, &, EVENT

Concurrent VHDL Code: Structural code, Dataflow, WHEN ..ELSE, WITH .. SELECT .. WHEN.

BCD to 7 segment decoder

Sequential VHDL Code: PROCESS, Sensitivity list, IF .. THEN .. ELSIF .. ELSE .. END IF; CASE .. IS .. WHEN => END CASE;

SR-Latch, D-Latch, D-Flip/Flop, D-F/F extra, Debounce circuit
Counter 1 8-bit binary counter Btn0 clocked, Counter 2 32-bit binary counter (50 MHz clock) + 4x8 mux.

Signals and Variables: The concept of delta delays. When to use signals or variables. Pitfalls of variables

Count ones example from Pedroni, Shift-register with signals and variables.
Multiplexed display - Create VHDL components for your own design

#10

State Machines: Mealy and Moore machines, State Diagram design, VHDL design with 1 -2 or 3 processes,
Abstraction levels - Gate, RTL, FSM, ASM, Ad-hoc

BCD counter -Toggle-button State Machine with 3 outputs (Toggle, Debounce and Pulse)

#11

Case study: Stopwatch

Stopwatch version 1 Ad hoc Design - Stopwatch version 2 - State Machine Design

#12

Arithmetic circuits: Add, Subtract, Multiply, Division, Conversion Binary to BCD

ALU Test - very simple calculator - Conversions Bin2Bcd and Bcd2Bin

#13

Memories: Flip/Flop memory, Distributed memory, Block RAM

Case - FIFO buffer.

#14

PWM versus PPM: Digital to Analogue Conversions and Analogue to Digital ditto

PWM vs Sigma Delta

#15

Case study: The Hilo Game

The HiLo Game

#16

Case study: Generic code - Packages - Procedures / Functions

#17

Yet to come: y

#18

Yet to come: y

#19

CPU - The Gnome: y

#20

PicoBlaze - The KCPSM3: y

#21

pBlazIDE - Integrated Develop Environment

#22

Case study - PicoBlaze:

	How to use the book or How will the book be used

	Wakerly describe the fundamental digital design topic with root in the TTL / CMOS days. The principle of State Machine design covered nicely with several examples. Three Hardware Description Languages used for examples namely: VHDL, Verilog and Abel.

Its impossible to create a course which fulfils all students needs and expectations - The basic goals will be VHDL and FPGA's.
VHDL called a Hardware Description Language and by using a Synthesize tool will it be possible to convert (some) VHDL code to real-life hardware.
Even your able to describe Digital Systems at rather high levels (Behavioural) must you have some basic understanding about the principles of digital design - Hence will there be links for those who might need extra knowledge.

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