![Return to DIG #8](../Exer_02_SRlatch/button1.jpg) |
D-Flip/Flop's the most
important sequential memory element which can be found in all
types of programmable logic and hence its used by default in all
types of synchronous designs.
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(1)
Understand the concept of a D-Flip/Flops
(2) Download the
Bit-file to your kit and tryout the functionality.
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This exercise present 3 different
implementations of D-F/F's. I prefer to use a multiplexer based
D-Latch instead of the more realistic circuit which can be found
in textbooks
A "real-life" D-F/F will normally be based on
three feedback loops or a similar CMOS based circuit.
Study
the D-F/F circuit
here
Or the
CMOS D-latch
here
(go to the bottom)
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![](exer3_15.gif)
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![bullet](../../../../_themes/clearday/acdbull1.gif) |
D-Flip/Flop
1 - Based on two "D-latches" |
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![](exer3_16.gif) |
The functionality of a
D-F/F can be obtained by connecting two D-Lathes in series. (See
the explanation below)
One D-Latch should be active low and the another active high.
What happens if the two latches changes places?
Note! The Mux implementation
with D-Latches
not advisable in practice, but nevertheless its works in test.
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![bullet](../../../../_themes/clearday/acdbull1.gif) |
D-Flip/Flop
2 -
Primitive D-F/F |
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The Schematic symbols
library of ISE offers several versions of D-F/Fs.
Check them out yourself or
learn more in the next exercise.
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![](exer3_17.gif)
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![](exer3_1.gif)
Extract from the Xilinx datasheet of Spartan 3E devices. |
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![bullet](../../../../_themes/clearday/acdbull1.gif) |
D-Flip/Flop
3 - The most common VHDL definition |
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A VHDL signal can be
connection to a number of Predefined Attributes.
'Event most likely the
only attribute you ever need unless your about write "advanced"
VHDL code.
The predefined functions
Rising_edge( )
and Falling_edge( )
are replacements for the similar 'event
expressions.
Read more about in the
documentations like
Hardi - page 51 or under the Language Templates.
Will the two versions of
D-F/F's used the same number of internal F/F's?
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![](exer3_18.gif)
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![](exer3_2.jpg)
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![](exer3_19.gif) |
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![](exer3_6.gif) |
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![bullet](../../../../_themes/clearday/acdbull1.gif) |
Download
here:
Bitfiles_etc_D_FF.zip
![bullet](../../../../_themes/clearday/acdbull2.gif) |
Try it yourself ... the functionality of the different implementations of
D-Flip/Flops. |
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![bullet](../../../../_themes/clearday/acdbull1.gif) |
Please note the
output from D-F/F3 after the download of the bit-file.
How come ....... ? |
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![](exer3_1.jpg) |
![bullet](../../../../_themes/clearday/acdbull1.gif) |
What's
inside a D-F/F - explanation of principles. |
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![](exer3_20.jpg) |
![bullet](../../../../_themes/clearday/acdbull1.gif) |
CMOS
D-Latches - Based on
transmission gates |
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![](../Exer_03_DLatch/Exer3_4.jpg) |
![](../Exer_03_DLatch/Exer3_4.gif) |
Learn more about the CMOS
D-latch
here
(go to the bottom) |