Design a digital
system with a 32-bit counter (synchronous Reset) in
combination with a 4x8-bit multiplexer
Use Sw(1:0) for selection.
The external clock-signal @ 50 MHz should be used
for the counter (NEXYS2 pin B8 / BASYS pin P54)
Design
a 8-bit Loadable Up/Down Counter with asynchronous
Clear
Just for the exercise - use a variable for the
Counter.
Design a
8-bit Loadable Up/Down Counter with synchronous
Reset
Just for the exercise - use a variable for the
Counter.
Design a
8-bit Counter with all edge-sensitive inputs.
This not a trivial problem to solve - and
perhaps comes this a bit to early in the course.
