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D-Flip/Flop's the most
important sequential memory element which can be found in all
types of programmable logic and hence its used by default in all
types of synchronous designs.
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(1)
Understand the concept of a D-Flip/Flop with Clock Enable,
Asynchronies Clear, Synchronies Reset
(2) Download the
Bit-file to your kit and tryout the functionality.
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In order to manage groups
of F/F in a digital design will you have to deal with things
like:
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Clock Enable |
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Asynchronous
Clear |
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Synchronous
Reset |
Most F/F's inside
programmable logic "born" with control signals for those
features.
All this and more can be
found in the libraries
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D-F/F
with Clock Enable |
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The Clock Enable necessary
in order manage clock distribution in larger digital systems
working with a synchronous Clk-pulses.
All F/Fs will receive the
same Clk-pulse but its not all of them you might want to react
on the Clk-pulse.
The most Common way to
"Implement" a Clock Enable signal in D-F/F shown at the right.
Alternative
implementations of Clock-Enable are shown below.
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D-F/F
with Asynchronous Clear |
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The Asynchronous Clear
signal, will set the Q output of a F/F to 0 (zero) without
waiting for a Clock-pulse.
You must include the
"Clear" signal sensitivity list of the process together with the
"Clk" signal. Moreover must the "Clear" be given the highest
priority in the if .. then .. elsif structure.
About names: In many
(most designs actually) will the name "Reset" be used for both
Asynchronous and Synchronous control.
Moreover will you find some confusion about
Clear and Reset in many textbooks.
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D-F/F
with Synchronous Reset |
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The Synchronous Reset
signal, will set the Q output of a F/F to 0 (zero) at the next
active Clock-pulse.
Since the "Reset" signal
depends on the "Clk" signal, there is no need to include it in
the sensitivity list of the F/F.
Will it be an error to
include it anyway?
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D-F/F
Clock Enable and
Synchronous Reset |
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Can a Clock Enable signal
controls a Synchronous Reset signal and will it be possible for
a Synchronous Reset to overrule a Clock Enable?
How will combinations of
Asynchronous Clear and Clock Enable works?
Some of these answers can
be read in the datasheets of the symbol-library. But you will
properly have to describe the functionality with a HDL code
anyway.
Simple circuits and tests
an easy way to find out what's possible and how things works in
practice.
Please note the "Preset"
signal which shown in these examples. How will you implement
this with HDL.
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Download here
Bitfiles_etc_DFF_Extra.zip
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Try it yourself ... the functionality of the different implementations of
Clock Enable and Clear / Reset.
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Will you be able to
control the Reset of DFF_CE_Sync_Reset with the Clock Enable
signal? |
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Alternative
implementations of Clock Enable |
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