No matter the order of assignments (<=) inside a process will the result be the same. Signals only gets values after the process ended and hence will both SigTest1 and SigTest2 result in (2-bit) shift-registers.

The same is true for the VarTest1 example below, whereas the VarTest2 will produce a 2-bit BUS due to the fact that a variable gets its value immediately after the assignment (:=)