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D-Latches not that often
used in digital designs - but they very important in concern
with PLC programming.
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(1)
Understand the concept of a D-Latch
(2) Download the
Bit-file to your kit and tryout the functionality.
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D-Latch
1 - The text book version |
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Basic implementation of a
D-Latch with NAND-gates.
Read more in
Wakerly 4ed - 7.2.4
Or read more in
Mark - 6.1.2
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D-Latch
2
- The standard schematic
symbol |
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This component can be found in the ISE
schematic libraryPlease note! QN
might give problems in practice, depending on the implementation
in the FPGA
Generally must the Boolean equation
QN = Not Q always be true
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D-Latch
3
- The
alternative Mux version (Read more
here) |
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The Mux-D-Latch not normally found in
textbooks (could it be my own idea?)
However will a multiplexer
normally present a 1- hazard and hence not fitted for
asynchronous feedback loops.
Conclusion - don't use
this in "real-life" even it works perfect in practice.
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D-Latch
4
- The
most common VHDL version |
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This the most common way to implement a
D-Latch with VHDL.
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What's actually behind a VHDL model???
The synthisise tool (most likely XTS)
use your VHDL code to figure out the functionality of the
circuit you wants.
In the end must this circuit use the
built-in components in the FPGA.
Note how the memory elements can set as
either FF or LATCH with active high or low inputs.
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A view from
the inside of a Spartan 3E FPGA
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CMOS
D-Latches - Based on
transmission gates |
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Learn more about the CMOS
D-latch
here
(go to the bottom) |
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