Titles
|
Topics - What to
learn
|
|
Test the kit |
A simple but effective
exercise to prove there's "hole through" - Schematic and
VHDL |
|
Combinatorial Logic |
Combinatorial
Logic - Multiplexers and Decoders. |
|
SR-Latch |
The S-R Latch
properly the most basic memory element in digital
designs |
|
D-Latch |
The D-Latch
integrated part of all FPGA's |
|
D-Flip/Flop |
D-Flip/Flops the most important storage element
in digital design (integrated in FPGA's) |
|
D-F/F Ce Clr Res |
D-Flip/Flops
comes with extra control pins in order to Enable Clock,
Clear or Reset |
|
Debounce - Circuit |
The best solution includes a
S-R Latch - this properly the second best solution of
Debouching |
|
|
|
|
Counter1 |
How to use Btn0 as a Clock
signal - |
|
Counter2..5 |
How fast is 50 MHz - watch
the blinking diodes. |
|
PWM vs. Sigma Delta |
What's the difference
between a PWM and a PPM output |
|
FIFO buffer |
Example of a "Logicore"
component |
