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About the book
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Last updated: 06-08-09

Consider your about to learn a new language like French: Would you start with a dictionary learning all the new words and then afterwards begin to use your skills forming sentences --- I believe not.
The same will be true for VHDL: The best way to learn VHDL will be to learn some basic elements of the language in combination with real world digital design. The book however seems to have the goal (as all other books of the topics) to give a complete description of the language.

VHDL was first intended for writing simulation models: If was first afterwards that the idea of writing code for synthesizing made it possible to describe a digital like you wanted it. After my opinion can you divide concept of VHDL in the following groups:

  1. The parts which benefits old times logic - for example was Emitter Coupled Logic (ECL) popular until the late 70ies but now it have historical interest. Some of the weak bits in std_logic and the Resolved vs. Unresolved concept fits into this category:
     
  2. The parts which intended for writing advanced generic simulation models - Its relative easy to write VHDL code with a fixed bit-width of busses, registers, counters etc. However will you, as an advanced programmer, prefer to write generic VHDL code where the bit-width open until the code implemented.
     
  3. The math, textio and file part - you can actually write all kind of programs with VHDL, but you will properly prefer Java, C++ or C#
     
  4. The basic parts for simulation - In order to write simple testbenches will you only need a few VHDL statements. Its important to realise that those part cant be used for synthesizing.
     
  5. The basic parts for synthesizing - Most of the VHDL constructions will useful for this purpose and you will properly be amazed what its possible to describe with relative few lines. However will you sometimes (read! often) face the problem that you can't get what you ask for, since the structures inside a programmable device limited.

This course will focus at the last  two parts in order to implement relative simple digital designs.

 
 

How the book will be used in the Course
 

   
 
Your free to read the book page by page - however must you be aware that the XiLinx ISE 11.1 only implement parts of the VHDL mention in the book. In order to save your time and effort, have I made some remarks of the most important keywords of each chapter.
This book origin from the time where ISE 6.1 was the newest tool available.

The topics and examples of the book do not come in the order that I would prefer for the Course. For instance will we need some relevant VHDL code in order to create test benches which first presented in chapter 6.

In appendix B will you find descriptions of Xilinx CPLD and FPGA devices - The Spartan 3 serie is still relevant, however must you visit Xilinx homepage to learn about the Spartan 3AN, Spartan 3E and Spartan 3A families.

 
Chap.

What's important and relevant.
1 Introduction:

The chapter is OK -  how ever must you be aware that the actual design-flow set by the XiLinx ISE 11.1

2 Code structure:

Library - Entity - Architecture  -  All VHDL designs consist of modules / components - the Entity defines the connections between the Architecture inside the module and "the world".

If you need internal connections (Signal) must they be defined before the begin keyword in the Architecture -  (Temp signal at page 21
The examples describes how combinatorial logic and sequential elements (Latches and Flip/Flops) can be created with VHDL.
3 Data types:

Don't spend that much time with this chapter - the content correct but: XiLinx ISE and the Simulator prefer the type Std_Logic and Std_Logic_Vector for Entities. For internal signals could the type Integer however be useful.

The book claims at page 37 that Std_Logic_Vector not useful for arithmetic operations - this not true.

The conversion functions - Conv_Integer( xxx) and Conv_Std_Logic_Vector( yyy,n) will enable you to switch between the two types.

Arrays could be useful if you want to define a storage like a RAM or ROM. Too bad will ISE tool properly not give you the best solution this way and you should instead use the IP coregenerator.

Enumerated types will be introduced together with State Machines.

4 Operators and Attributes:

Lots of information in this chapter, however will generic VHDL components not be the major part of this course. The most important facts mention below.

The difference between signals and variables can be seen by the assignments:   <= for signals and := for variables.
Instead of a fixed vector assignment like   x <= "00000000" can   x <= (others =>'0') be used.
The concatenation operator & very useful when it comes to combine vectors and signal to new combinations.

Page 52 - Clk'event and Clk='1'  and Rising_edge( Clk) will the most important attributes.

 
5 Concurrent Code:

Digital logic is divided in two groups: Combinatorial logic and Sequential logic.
The same is true for VHDL where statements could either be Concurrent or Sequential. Most of the examples in this chapter could be applied to the NEXYS kit as well

All code written inside the Architecture will be Concurrent (no matter which order you write them will the always be executed in the correct order). Note that a process can be seen as one Concurrent statement - but what's happens inside a process not Concurrent

 
6 Sequential Code:

The code inside a Process is executed in a sequential manner - just like a C++ or Java program. If you decide to use Variables instead of signals will you be able to write "normal" computer programs. How ever will there still be some "deep pitfalls".

Sequential Code comes natural when you what's to describe Digital system which involves F/F

 
7 Signals and Variables:

One of the key-stones about VHDL will be to understand the difference between Signals and Variables.

 
8 State Machines:

All Digital Systems of importance based are based at the principles of State Machines.

 
9 Additional Circuit Design:

The chapter is OK -  however will not examples be used

 
10 System Design - Packages and Components:

The chapter is OK -  however will not examples be used

 
11 System Design - Functions and Procedures:

The chapter is OK -  however will not examples be used

 
12 Additional System Design:

The chapter is OK -  however will not examples be used
 
 

 
   
       

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