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Sequential VHDL Code
 

 Topics:

Last updated: 13-08-09

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 Combinatorial processes
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Different implementations of 4x1 multiplexer with Sequential code

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The concept of Latches and Flip/Flops
 

 More information:

bulletPedroni chapter 6 - Sequential Code
bulletIn order to get logic implemented in hardware must you obey certain rules (which not always clearly defined)
Specially if you want to implement sequential logic will the advice be a Process with sensitivity-list - your free to try the example of the which not uses this structure and they will mostly work ok.
bulletThe real problem behind using wait until statement discussed in section 6.9 bad clocking.
 
bulletCombinatorial logic versus Sequential logic

A combinatorial circuit will consist of number of inputs which produces one or more outputs. The same combination of input values will always produce the same output combination.

Its at a golden rule never to make feedback loops between the outputs and the inputs of the same combinatorial circuit. I fact will the ISE software give you warnings in case you do this (by purpose or accident).

Nevertheless are those feedback circuits important in order to produce internal memory inside a digital circuit. Sequential elements like Latches and Flip/Flops are formed by the use of feedback loops.
 
 Exercises / Problems:
bullet Exercise: SR-Latch  - One of the basic storage elements formed by a single feedback loop. This circuit not integrated in CPLD's or FPGA's.
But a SR-Latch can be formed with combinatorial logic and the feedback loop (which however bound to give warnings)
bullet Exercise: D-Latch - can be found as an integrated part of FPGA's (The same element can also act as a F/F)
bullet Exercise: D-Flip/Flop - Can be found integrated inside all CPLD's and FPGA's (Several thousands)
bullet Exercise: D-Flip/Flop extra - Introducing Clock Enable, Synchronous Reset and Asynchronous Clear
bullet Exercise: Debounce-circuit - Some of the exercises will properly have revealed a problem with the press-buttons of the kit.
Create a VHDL source of the circuit shown or create your own Debounce-circuit.
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Exercise: Counter 1 - The difference between asynchronies  Clear and synchronous Reset 

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Exercise: Counter 2 - Test the difference between 50 MHz, 50 Hz and 25 Hz

 
   
 
   
   
bulletProblem 6.1 Event Counter  (Pedro page 121)
   
 
More information in the book
bulletProblem 6.2 Shift Register  (Pedro page 121)
   
 
More information in the book
bulletProblem 6.3 Priority Encoder  (Pedro page 121)
   
 
More information in the book
       

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