#5 >>> First test bench <<<

First Test Bench

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Last updated: 16-08-09

Introducing the concept of testing

Automatic generated Test bench (and the corrections needed)

VHDL code for simulation - mostly wait for statements.

The ISIM program - the build in simulation tool of the ISE

A more advanced simulation tool - Modelsim can be downloaded (Free starter version) and called from the ISE

In order to verify the functionality of your design must you create a Test Bench. VHDL was originally created for the purpose of writing simulations model and hence will it be easy to create clock generators and stimuli for the inputs.

More advanced Test Benches will be able read stimuli from files and compare with the expected outputs (from a file as well)
In fact do you got all the features which can be found in a "normal" high level program language like C++, Java etc.

The simulation can either be:
Behavioural Simulation where all logic ideal (no delays, only pure Boolean logic)
Post-Route Simulation where the expected delays from the FPGA taken into account.

Exercises / Problems:

Combinatorial Logic - A short presentation of Combinatorial logic

Test bench = VHDL module with an empty Entity




Test bench with analogue signals - too bad can't this be shown as curves

Problem 2.1 Multiplexer (Pedro page 22)

Continue in the book

Problem 2.2 Logic gates (Pedro page 24)

Continue in the book

Exercise - (Pedro page 6)



	more in the book