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4x1 Multiplexer - Sequential VHDL Code
 
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The Process will appear as a concurrent statements seen from the outside.

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In other words:  If you got two or more processes will they always be executed in the correct order.

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The sensitivity-list indicates which signals allowed to trigger the process.
You will learn from the literature that the sensitivity-list can be replaces by wait on and wait until statements.
This however not acceptable by the synthesize tool.

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The statements inside a process considered sequential - hence are they executed in the order they are written.

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If the process meant to describe combinatorial logic (Combinatorial process) must all input signals and internal signal be in the sensitivity-list.

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Your allowed to define variables inside a process - note! shared variable could be used as well.

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The difference between signal an variables important to understand.
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A signal known by the <= assignment and a signal will first get its value when the process concludes.

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A variable known by the := assignment a variable will get its value immediate with the assignment.

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Consider if you was forced to convert Var0 to be a signal - which changes should be made?