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Case Is

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4x1 Multiplexer - Sequential VHDL Code
 
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The Case statement of the process similar to the concurrent with .. select statement.

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However are you allowed to add several statements for each selection (delimited with ;)

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The selection values must be constants.

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Your allowed to separate more constants with the | operator.

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You must assign selections for each combination of the selection signal (in this case Sbus)

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You can use When others to cover the rest of combinations.

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Even if you used When "11" instead of When others will you get an error in the example (how come?)
 

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You will often use the Case statement to implement state machines.
 

 

 
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Note - how the two "Wires" S1 and S0 are concatenated into a two-bit Sbus with the & operator.

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Sin will be the integer representation of the Sbus