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If Then Else

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4x1 Multiplexer - Sequential VHDL Code
 
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The Process can be triggered by integer as well

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However can a process not be triggered by single bits of a vector like Sbus(1) for instance.

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In contrast to concurrent code are you allowed to assign values to a signal / variable more then once.

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The last assigned value will also be the final value for the signal.

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The variable of a variable will change for each assignment.

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If your planning to create combinatorial logic will a default assignment in the start avoid implied latches.

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For each if statement must there be an end if.

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By using the combined elsif statement can you reduce the number of end if.
 

 

 
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Note - how the two "Wires" S1 and S0 are concatenated into a two-bit Sbus with the & operator.

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Sin will be the integer representation of the Sbus