[ Home ] [ Up ] [ Stimuli demo ] [ Clock generator ] [ First Test Bench ] [ Up ]
Topic:
Last updated: 03-08-09
Introducing the automatic VHDL Test Bench of ISE
-----
The ISIM offers you several options like: Adding internal signals of components inside the UUT Adding dividers between signals Changing the Radix of buses. Creating virtual busses Debugging of the VHDL source