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4x1 Multiplexer - Concurrent VHDL Code
 
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All statements between Begin .. End of the Architecture section are by definition concurrent.

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This implies that the order of statements doesn't matter - they will always be executed in correct order.

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Your only allowed to assign a signal once - otherwise will you get an error like: Multiple drivers for output xxx

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A Process is a Concurrent statements seen from outside - whereas the inside considered sequential.