The Register Transfer Level (or RTL Design) indicates the fact that VHDL used to describe Flip-Flops and Combinatorial logic.

In order to write the VHDL code must the Boolean equations first be available. This will properly involve Carnaugh maps or Boolean algebra. In real life project will you seldom select this approach to the solution.
 

Note!

The Boolean equations derived as "minimum cost" basic.
(all unused states will be don't care)

The opposite will be "minimum risk"

Take a close look at the state coding.
what's smart about this?