With a Hardware Description
Language like VHDL can you describe any circuit
structure and functionality you would like to have
(for instance a Carry Look a Head adder).
But if your planning to
implement the design in a FPGA - the name of the
game changes.
The resources inside a FPGA (XiLinx, Altera, Latice
etc) trimmed for optimal performance and the
synthesise tool will use your description to choose
the best implementation.
In the case Adders - Use a
simple behavioural description of the adder and your
getting the best performance and result.
