The best way (in many ways) to implement a 32-bit Adder simply to add vectors of the size N+1 where N the account of bits in the largest number.

 

The result quite amazing - only half the cost of Ripple-Carry Adder.

And also a more efficient use of slices (all four LOT tables in use)

 

The simulation reveals that we actually now dealing with a Carry Look-a-head Adder, even the sum bits a bit random to watch.

An interesting detail also the fact that Cout arrives before the most significant Sum-bit - namely Sum[31]

The Propagation delay now say - 10 nsec

For the Ripple Carry Adder was it around 45 nsec.

I order to understand how this possible must we consult the technically documents of the FPGA.

More precise UG331.pdf which the user guide for the Spartan 3 family

Please note how a Full Adder can be build with two Half Adders and a single OR

Also note how a Half Adder produces the signal which needed for the Look-Ahead carry

A smart redesign of the Full Adder makes it possible to omit (save) the AND-gate for Carry generation and the dedicated multiplexer used for the Carry propagation will in the end be faster then logic.

The First XOR will be implement as logic in a LUT, whereas the Sum output will come from a dedicated XOR-component.

Please consult the UG331.pdf for more details.

The structure of the FPGA gives a Carry Chain which placed as vertical-lines between the CLBs.

The Logic and Memory slice can also work together well.