FTCLE is a toggle/loadable flip-flop
with toggle and clock enable and asynchronous clear.
When the asynchronous clear input (CLR)
is High, all other inputs are ignored and output Q is
reset Low.
When load enable input (L) is High and
CLR is Low, clock enable (CE) is overridden and the data
on data input (D) is loaded into the flip-flop during
the Low-to-High clock (C) transition.
When toggle enable (T) and CE are High
and L and CLR are Low, output Q toggles, or changes
state, during the Low- to-High clock transition.
When CE is Low, clock transitions are
ignored.
The flip-flop is asynchronously cleared, output Low,
when power is applied.
