No10_HiLo_game3 Project Status (08/09/2009 - 23:00:45) | |||
Project File: | No10_HiLo_game3.ise | Implementation State: | Placed and Routed |
Module Name: | The_HiLoGame3 |
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Target Device: | xc3s500e-4fg320 |
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Product Version: | ISE 11.2 |
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All Signals Completely Routed |
Design Goal: | Balanced |
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All Constraints Met |
Design Strategy: | Xilinx Default (unlocked) |
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0 (Setup: 0, Hold: 0) (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 138 | 9,312 | 1% | ||
Number of 4 input LUTs | 174 | 9,312 | 1% | ||
Number of occupied Slices | 111 | 4,656 | 2% | ||
Number of Slices containing only related logic | 111 | 111 | 100% | ||
Number of Slices containing unrelated logic | 0 | 111 | 0% | ||
Total Number of 4 input LUTs | 190 | 9,312 | 2% | ||
Number used as logic | 174 | ||||
Number used as a route-thru | 16 | ||||
Number of bonded IOBs | 31 | 232 | 13% | ||
Number of BUFGMUXs | 1 | 24 | 4% | ||
Average Fanout of Non-Clock Nets | 3.65 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | ||||||
Translation Report | Current | sų 9. aug 19:00:36 2009 | ||||
Map Report | Current | sų 9. aug 19:00:49 2009 | ||||
Place and Route Report | Current | sų 9. aug 19:01:10 2009 | ||||
Power Report | ||||||
Post-PAR Static Timing Report | Current | sų 9. aug 19:01:12 2009 | ||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | sų 9. aug 19:02:08 2009 | |
Post-Place and Route Simulation Model Report | Out of Date | sų 9. aug 19:01:29 2009 |