SINUSGEN1 Project Status
Project File: SinusGen1.ise Current State: Programming File Generated
Module Name: PPM_output
  • Errors:
 
Target Device: xc3s100e-4tq144
  • Warnings:
 
Product Version: ISE 9.2.04i
  • Updated:
ma 17. nov 16:10:21 2008
 
SINUSGEN1 Partition Summary
No partition information was found.
 
Device Utilization Summary
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 19 1,920 1%  
Number of 4 input LUTs 18 1,920 1%  
Logic Distribution     
Number of occupied Slices 10 960 1%  
    Number of Slices containing only related logic 10 10 100%  
    Number of Slices containing unrelated logic 0 10 0%  
Total Number of 4 input LUTs 18 1,920 1%  
Number of bonded IOBs 20 108 18%  
Number of GCLKs 1 24 4%  
Total equivalent gate count for design 368      
Additional JTAG gate count for IOBs 960      
 
Performance Summary
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map ReportCurrentma 17. nov 15:30:40 200801 Warning3 Infos
Place and Route ReportCurrentma 17. nov 15:30:45 2008000
Static Timing ReportCurrentma 17. nov 15:30:48 2008002 Infos
Bitgen ReportCurrentma 17. nov 15:30:52 2008000